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| LCX018AK 1.8cm (0.7-inch) NTSC/PAL/WID Color LCD Panel For the availability of this product, please contact the sales office. Description The LCX018AK is a 1.8cm diagonal active matrix TFT-LCD panel addressed by the polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel provides fullcolor representation in NTSC/PAL/WID mode. RGB dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. Features * Number of active dots: 240,000 (0.7-inch; 1.8cm in diagonal) * Horizontal resolution: 400 TV lines * High optical transmittance: 4.4% (typ.) * High contrast ratio with normally white mode: 200 (typ.) * Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible) * High quality picture representation with RGB delta arranged color filters * Full-color representation * NTSC/PAL/WID compatible * Up/down and/or right/left inverse display function * Side-black function * 16:9 and 4:3 aspect switching function Element Structure * Dots 16:9 display: 1068.5 (H) x 225 (V) = 240,412 4:3 display: 803.5 (H) x 225 (V) = 180,787 * Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98521-PS Block Diagram 2 Up/Down and/or Right/Left Inversion 4:3/16:9 Control Circuit PSIG HST HCK1 HCK2 7 9 10 V Shift Register (Bidirectional Scanning) 11 Input Signal Level Shifter Side-Black Control Circuit WID 8 16 15 14 18 RGT VST VCK1 VCK2 PCG DWN 17 H Shift Register (Bidirectional Scanning) -2- COM Pad EN 13 6 19 12 5 4 3 HVDD VVDD VSS SIG3 SIG2 V Shift Register (Bidirectional Scanning) SIG1 1 COM LCX018AK LCX018AK Absolute Maximum Ratings (Vss = 0V) * H driver supply voltage HVDD * V driver supply voltage VVDD * H driver input pin voltage HST, HCK1, HCK2 RGT * V driver input pin voltage VST, VCK1, VCK2 CLR, EN * Video signal input pin voltage GREEN, RED, BLUE * Operating temperature Topr * Storage temperature Tstg -1.0 to +17 -1.0 to +17 -1.0 to +17 -1.0 to +17 -1.0 to +15 -10 to +70 -30 to +85 V V V V V C C Operating Conditions (Vss = 0V) * Supply voltage HVDD 13.5 0.5 V VVDD 13.5 0.5 V * Input pulse voltage (Vp-p of all input pins except video signal input pins) Vin 3.0V or more Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol COM PSIG SIG1 SIG2 SIG3 HVDD WID RGT HST HCK1 HCK2 VSS EN VCK2 VCK1 VST DWN PCG VVDD SOUT Common voltage of panel Improvement signal for uniformity Video signal (Green) to panel Video signal (Red) to panel Video signal (Blue) to panel Power supply for H driver Aspect-ratio switching (H: 16:9, L: 4:3) Drive direction pulse for H shift register (H: normal, L: reverse) Start pulse for H shift register drive Clock pulse for H shift register drive Clock pulse for H shift register drive GND (H, V drivers) Enable pulse for gate selection Clock pulse for V shift register drive Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: normal, L: reverse) Improvement pulse for uniformity Power supply for V driver H, V shift register drive confirmation -3- Description LCX018AK Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is shown below. (The resistor value: typ.) (1) SIG1, SIG2, SIG3, SID HVDD From H driver Input 1M (2) HCK1, HCK2 VVDD 250 HCK1 1M 250 HCK2 250 1M 250 Signal line Level conversion circuit (2-phase input) (3) HST HVDD 250 Input 1M 250 Level conversion circuit (single-phase input) (4) RGT, WID HVDD 2.5k Input 1M 2.5k Level conversion circuit (single-phase input) (5) VCK1, VCK2 VVDD 250 VCK1 1M 250 VCK2 250 1M 250 Level conversion circuit (2-phase input) (6) VST, DWN, EN VVDD 2.5k Input 1M 2.5k Level conversion circuit (single-phase input) (7) PCG VVDD 250 Input 1M 250 Level conversion circuit (single-phase input) (8) COM VVDD Input 1M LC -4- LCX018AK Input Signals 1.Input signal voltage conditions (Vss = 0V) Item H driver input voltage (HST, HCK1, HCK2, RGT, WID) V driver input voltage (VST, VCK1, VCK2, DWN, PCG, EN) Video signal center voltage Common voltage of panel (Low) (High) (Low) (High) Symbol VHIL VHIH VVIL VVIH VVC VCOM Min. -0.30 2.7 -0.30 2.7 5.8 Typ. 0.0 3 0.0 3 6.0 Max. 0.30 5.5 0.3 5.5 6.2 Unit V V V V V V VVC - 0.4 VVC - 0.25 VVC - 0.1 Item Video signal input range1 Symbol (VDD = 12.0V) Vsig Min. VVC - 4.0 VVC - 4.0 0.5 Typ. Max. VVC + 4.0 VVC + 4.0 Unit V V V Uniformity improvement signal PSIG input voltage Vpsig Video signal and uniformity improvement signal input white level 1 Video input signal should be symmetrical to VVC. VsigL Supplement) Video signal and uniformity improvement signal input range are set within the range shown below for VDD and VSS. Also, video signal white level is defined for VVC as shown below. VDD VDD - 1.8 VsigL White level VVC VsigL Video signal input range Max. VDD - 1.8 [V] Min. VSS + 1.3 [V] VDD + 1.3 VSS -5- LCX018AK 2. Clock timing conditions (Ta = 25C) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn2 rise time HCK Hckn2 fall time Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time Vckn2 rise time VCK Vckn2 fall time Vck1 fall to Vck2 rise time Vck1 rise to Vck2 fall time Enb rise time ENB Enb fall time Vck rise/fall to Enb rise time Enb pulse width Pcg rise time PCG Pcg fall time Pcg fall to Vck rise/fall time Pcg pulse width Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVckn tfVckn to1Vck to2Vck trEnb tfEnb tdEnb twEnb trPcg tfPcg toVck twPcg -20 -20 -- -- 2150 5950 -- -- -1050 2450 0 0 -- -- 2200 6000 -- -- -1000 2500 -5.5 49 4.5 59 -15 -15 0 0 35 80 45 90 Min. Typ. Max. 30 30 55 100 30 30 15 15 100 100 14.5 69 100 100 20 20 100 100 2250 6050 20 20 -950 2550 ns s ns Unit 2 Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 3.72MHz, fVckn = 7.81kHz) -6- LCX018AK Hst 10% trHst Waveform 90% 90% 10% tfHst Conditions * Hckn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst Hst data set-up time tdHst Hst 50% 50% Hck1 50% 50% Hst data hold time thHst tdHst thHst 90% 10% * Hckn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn2 rise time Hckn2 fall time HCK 90% trHckn 2 Hckn 10% tfHckn 3 to1Hck Hck1 trHckn tfHckn * Hckn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 60ns thHst = -120ns Hck1 fall to Hck2 rise time 50% 50% 50% 50% * tdHst = 60ns thHst = -120ns Hck1 rise to Hck2 fall time Hck2 to2Hck to2Hck to1Hck -7- LCX018AK Vst 10% trVst Waveform 90% 90% 10% tfVst 50% 50% 50% Conditions * Vckn2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns tfVst 3 50% Vst Vck1 Vst data hold time thVst tdVst thVst 90% 10% * Vckn2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns Vckn2 rise time trVckn Vckn 90% 10% Vckn2 fall time VCK Vck1 fall to Vck2 rise time Vck1 rise to Vck2 fall time Enb rise time tfVckn trVckn tfVckn 50% * Vckn2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVst = 32s thVst = -32s 3 to1Vck Vck1 50% 50% 50% * tdVst = 32s thVst = -32s to2Vck Vck2 to2Vck to1Vck 90% trEnb Enb 90% 10% 10% Enb fall time ENB tfEnb Vck tfEn trEn 50% Vck rise/fall to Enb rise time tdEnb Enb 50% twEnb 50% Enb pulse width twEnb 4 tdEnb Pcg rise time Pcg fall time PCG Pcg fall to Vck rise/fall time Pcg pulse width trPcg Vck 50% tfPcg toVck twPcg Pcg 50% 50% twPcg toVck 4 3 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means -. The black dot at an arrow ( ) indicates the start of measurement. -8- LCX018AK Electrical Characteristics (Ta = 25C, HVDD = 13.5V, VVDD = 13.5V) 1. Horizontal drivers Item Input pin capacitance Hckn Hst Input pin current Hck1 Hck2 Hst, Wid, Rgt Video signal input pin capacitance Current consumption Symbol CHckn CHst IHck1 IHck2 IRgt Csig IH -450 -900 -130 Min. Typ. 8 8 -190 -200 -25 150 3.5 200 6 Max. 13 13 Unit pF pF A A A pF mA Hckn: Hck1, Hck2 (3.72MHz) Hck1 = GND Hck2 = GND Hst, Wid, Rgt = GND Condition 2. Vertical drivers Item Input pin capacitance Vckn Vst Input pin current Vck1 Vck2 Vst, En, Dwn, Pcg Current consumption Symbol CVckn CVst IVck1 IVck2 IVst, IEn IV -450 -900 -130 Min. Typ. 8 8 -190 -200 -25 1.0 2.0 Max. 13 13 Unit pF pF A A A mA Vck1 = GND Vck2 = GND Vst, En, Dwn, Pcg = GND Vckn: Vck1, Vck2 (7.87kHz) Condition 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) Symbol PWR Min. Typ. 60 Max. 120 Unit mW 4. COM input resistance Item COM - Vss input resistance Symbol Rcom Min. 0.5 Typ. 1 Max. Unit M 5. Improvement signal for uniformity Item Improvement signal for uniformity Symbol CPSIGon -9- Min. -- Typ. 7 Max. 10 Unit nF LCX018AK Electro-optical Characteristics Item Contrast ratio Optical transmittance R X Y Chromaticity G X Y B X Y V90 V-T characteristics 25C 60C V50 25C 60C V10 Half tone color reproduction range ON time Response time OFF time Flicker Image retention time Optimum Vcom voltage 25C 60C R vs. G B vs. G 0C 25C 0C 25C 60C 60min. 25C 60C Symbol CR25 CR60 T Rx Ry Gx Gy Bx By V90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT60 Vcomopt 7 8 9 6 5 4 3 2 Measurement method 1 Min. 80 80 3.8 0.580 0.300 0.250 0.550 0.105 0.070 1.1 1.0 1.5 1.4 2.2 2.1 -- -- -- -- -- -- -- -- 5.60 (Ta = 25C, NTSC mode) Typ. 200 200 4.4 0.620 0.340 0.290 0.590 0.140 0.110 1.5 1.3 2.0 1.8 2.7 2.5 -0.10 0.10 25 8 65 20 -- -- 5.75 Max. -- -- -- 0.660 0.380 0.330 0.630 0.175 0.150 2.2 2.1 2.5 2.4 3.2 3.1 -0.25 0.45 100 40 150 60 -40 20 5.90 dB s V ms V V CIE standards % Unit -- - 10 - LCX018AK Back Light Back light Luminance Meter 3.5mm LCD panel Measurement Equipment Back light: color temperature 8500K, +0.004uV (25C) Back light spectrum (reference) is listed on another page. Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) ... (1) L (Black) L (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.5V Both luminosities are measured by System I. - 11 - LCX018AK 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= L (White) x 100 [%] ... (2) Luminance of Back Light L (White) is the same expression as defined in the "Contrast Ratio" section. 3. Chromaticity Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses Chromaticity of x and y on the CIE standards here. Signal amplitudes (VAC) supplied to each input R input R Raster G B 0.5 4.5 4.5 G input 4.5 0.5 4.5 B input 4.5 4.5 0.5 (Unit: V) 4. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V90, V50 and V10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. Transmittance [%] 90 50 10 V90 V50 V10 5. Half Tone Color Reproduction Range Half tone color reproduction range of the LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G, B raster modes which correspond to 50% of transmittance, V50R, V50G and V50B respectively. V50RG and V50BG, the voltage differences between V50R and V50G, V50B and V50G, are simply given by the following formula (3) and (4) respectively. V50RG = V50R - V50G ... (3) V50BG = V50B - V50G ... (4) VAC - Signal amplitude [V] 100 V50RG V50BG Transmittance [%] 50 R raster G raster B raster 0 V50R V50B V50G VAC - Signal amplitude [V] - 12 - LCX018AK 6. Response Time Response time ton and toff are defined by the formula (5) and (6) respectively. ton = t1 - tON ... (5) toff = t2 - tOFF ... (6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. Input signal voltage (waveform applied to the measured pixels) 4.5V 6V 0.5V 0V Light transmission output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff 7. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in System II. AC component } F [dB] = 20 log { DC component ... (7) R, G, B input signal condition for gray raster mode is given by Vsig = 6 V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve. 8. Image Retention Time Image retention time is given by the following procedures: Apply monoscope signal to the LCD panel for 60 minutes and then change monoscope signal to gray scale signal (Vsig = 6 VAC (V); VAC = 3 to 4V) so as to give the maximum image retention. Hold input signal VAC. The time of the residual image to disappear gives the image retention time. Monoscope signal conditions: Black level Vsig = 6 4.5 or 6 2.0 [V] 4.5V White level (shown in the right figure) 2.0V Vcom = 5.6V 6V 2.0V 4.5V 0V Vsig waveform - 13 - LCX018AK 9. Method of Measuring the Optimum Vcom There are two methods of measuring the optimum Vcom using the photoelectric element. 9-1. Method of Measuring Flicker In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value at this time is taken to be the optimum Vcom. 9-2. Method of Measuring Contrast In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom. Example of Back Light Spectrum (Reference) 0.6 0.4 0.2 0 380 480 580 Wave length 380 - 780 [nm] 680 780 - 14 - Description of Operation 1. Color Coding The shaded area is used for the dark border around the display. LCX018AK Dot Arrangement (16:9) EVEN = 1083 dots ODD = 1083 dots EVEN = 7 dots ODD = 8 dots 1 2 3 355 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW EVEN = 1069 dots ODD = 1068 dots (Effective 15.493mm) 356 357 EVEN = 7 dots ODD = 7 dots DR1 DR2 GATE SW GATE SW GATE SW GATE SW DL1 DL2 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW 2 dots 225 dots (Effective 8.775mm) 2 dots - 15 - BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR 1 BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB 2 RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR 3 BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB 4 RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR 224 BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB 225 RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR LCX018AK LCX018AK Dot Arrangement (4:3) EVEN = 1083 dots ODD = 1083 dots EVEN = 7 dots ODD = 8 dots EVEN = 803 dots ODD = 804 dots (Effective 11.651mm) 4:3 Area 44 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW EVEN = 133 dots ODD = 132 dots EVEN = 133 dots ODD = 132 dots Side Black 311 312 313 314 356 357 EVEN = 7 dots ODD = 7 dots Side Black 2 45 46 47 DL1 DL2 1 DR1 DR2 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW 2 dots B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R 1 B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB 225 dots (Effective 8.775mm) 2 dots - 16 - 2 RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R 3 B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB 4 RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R 224 B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB 225 RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG BRGB RGBRGB RGB RGB RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRG BRGB R RG B R GB R G B RG B RG B RG B RG B RG B RG B RG B RG B R G B RGB R GB RG B RG B R B RGB R GB RG BRG BRGB RGBRG B RGBRGBRGB RGBRGBRGBRG B RGB RGBRGB RGB RGB RGBRGBRGB LCX018AK LCX018AK 2. LCD Panel Operations [Description of basic operations] The basic operations of the LCD panel are shown below based on the wide-display mode. * A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 225 gate lines sequentially in every single horizontal scanning period. * A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuit, applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period. * Vertical and horizontal shift registers address one pixel, and then dot Thin Film Transistors (TFTs; two TFTs for one dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 480 x 1068.5 dots to display a picture in a single vertical scanning period. * The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold (S/H) pulses follow the same 1.5-bit offset scheme. * The video signal must be input with polarity-inverted system in every horizontal cycle. * Timing diagrams of the vertical and the horizontal display cycle are shown below. (1) Vertical display cycle (down-direction scanning) VD VST VCK1 1 2 3 223 224 225 VCK2 Vertical display cycle (2) Horizontal display cycle (16:9) BLK HST HCK1 HCK2 1 2 3 355 356 357 Horizontal display cycle (3) Horizontal display cycle (4:3) BLK HST HCK1 HCK2 1 2 3 267 268 269 Horizontal display cycle - 17 - LCX018AK [Description of operating mode] The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. * Right/left inverse mode * Up/down inverse mode * 4:3 display mode with side-black display These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below: WID RGT H H L L H L H L Mode 16:9 right scan 16:9 left scan 4:3 right scan 4:3 left scan DWN H L Mode Down scan Up scan The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin block upside. * The analog signal (PSIG) to display side-black shall be input by 1H inversion synchronized with the signal. 3. 3-dot Simultaneous Sampling (RGB Simultaneous Sampling) Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. The block diagram of the delaying procedure using sample-and-hold method is as follows. The LCX018 has the right/left inverse function. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between SIG2 and SIG3 signals. SIG2 S/H CK2 S/H CK3 S/H CK1 S/H CK3 S/H CK3 AC Amp 4 SIG2 SIG1 AC Amp 3 SIG1 SIG3 AC Amp 5 SIG3 HCKn CK2 CK1 CK3 - 18 - LCX018AK LCX018AK Example of Color Filter Spectrum (Reference) 100 Color Filter Spectrum R 80 G B 60 Transmittance [%] 40 20 0 400 500 Wavelength [nm] 600 700 - 19 - LCX018AK Color Display System Block Diagram +12.0V +4.5V +3.0V +13.5V PSIG Composite video Buff. Y/C RED Y/color difference GREEN BLUE COM HST HCK1 LCD panel NT/PAL/WID LCX018AK CXA2543R HCK2 VST Serial data VCK1 VCK2 ENB PCG DWN WID (Refer to CXA2543R data sheet.) RGT Control circuit - 20 - LCX018AK Notes on Handling (1) Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in high temperature or in high humidity, which results in panel damages. - 21 - LCX018AK Package Outline Unit: mm 2.9 0.15 Thickness of the connector 0.3 0.05 10.5 0.05 1.3 0.3 4 (40.2) 1 3 4-R 59.2 0.8 1.0 2 5 19.0 0.15 Incident light Polarizing Axis 6 Incident light 6 Output light Polarizing Axis Active Area 7.6 0.25 (8.8) (15.5) 11.0 0.25 22.0 0.15 No 1 2 0.5 0.15 Description FPC Molding material Outside frame Reinforcing board P 0.5 0.02 x 19 = 9.5 0.03 + 0.04 0.35 - 0.03 3 3.0 0.3 4 PIN1 0.5 0.1 PIN 20 5 Reinforcing material 6 Polarizing film weight 2g electrode (enlarged) The rotation angle of the active area relative to H and V is 1. - 22 - |
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